In our last post, we explored the Nordic VPR RISC-V processor through the lens of the peripheral processor (PPR) on the nRF54H20. While we demonstrated how the application processor can configure and start a VPR processor, we stopped short of demonstrating any further communication between them. Most meaningful use-cases of the PPR and the FLPR,...
VPR (pronounced “Viper”) is Nordic Semiconductor’s first RISC-V processor, landing in the new nRF54H and nRF54L lines of SoCs after their initial announcements in April and October of 2023 respectively. Readers of this blog are familiar with my long-running obsession interest in RISC-V (see my RISC-V Tips and RISC-V Bytes series). However,...
Nordic Semiconductor recently made their new IoT prototyping platform, the Thingy:91 X, generally available. The Thingy:91 X is an upgrade to their existing prototyping platform, the Thingy:91, replacing the nRF9160 System-in-Package (SiP) with an nRF9151 SiP, the nRF52840 System-on-Chip (SoC) with an nRF5340 SoC, and adding the nRF7002...
Well, not this one. But this one is! How? Let’s take a closer look at Bluesky and the AT Protocol that underpins it. Note: I communicated with the Bluesky team prior to the publishing of this post. While the functionality described is not the intended use of the application, it is known behavior and does not constitue a vulnerability disclosure...
The ESP32-S3 is a popular microcontroller (MCU) for a variety of reasons, such as its support for external pseudostatic RAM (PSRAM). One of its lesser known features is its Universal Serial Bus (USB) On-The-Go (OTG) controller. The previously released ESP32-S2, as well as the new ESP32-P4, also have USB OTG support, with the latter having two...
Three weeks ago I wrote the following draft of a blog post entitled “Is It Better to Fail Spectacularly?”. I am having a lot of doubts. I’ve been training for the Chicago Marathon in earnest since June, but in reality the preparations began a year ago when I was accepted based on my qualifying time from the 2023 Ventura Marathon. I don’t have...
Isolating sensitive data and operations is a fundamental issue in computing. Ideally, we want to minimize the possibility of a software defect compromising the security of a device. However, in order for the software we write to be useful, it typically needs to interact with that sensitive data in some form or fashion. So how do we interact with...
Paul Graham’s Founder Mode essay, based on a recent talk from AirBnB founder Brian Chesky, has been getting quite a lot of attention over the past few days. It has prompted many a quote tweet, and founders, such as Bryan Cantrill of Oxide Computer, have started contributing their own thoughts to what founder mode means to them. Having held...
I frequently work with ESP32 microcontrollers (MCU), both at my day job and in my free time. These devices are very flexible, but like any microcontroller they are quite resource constrained in comparison to anything equivalent to or larger than a single-board computer. There are a few different variants of the ESP32 these days, but one of the...
I have spent the majority of my career in engineering roles at startups. Both at companies I have worked at, and in the general startup ecosystem, I have frequently heard some variation of the refrain “engineers are expensive, but wireframes are cheap”. While I align with the underlying sentiment that doing the least amount of work to get...
I have been very fortunate to have both worked alongside some incredible engineering leaders, as well as lead engineering teams myself. These experiences have primarily been in the context of startups that are growing rapidly in terms of both customers and employees. The longer I have worked in these environments, the more convinced I have become...
This post is the second in a RISC-V Bytes subseries on the PINE64 Pinecil soldering iron and development board. Previous and subsequent posts can be found under the RISC-V Bytes category. In the most recent Pinecil post, we walked through how to solder the header pins on the Pinecil breakout board. With the headers attached, we can now...
This post is the first in a RISC-V Bytes subseries on the PINE64 Pinecil soldering iron and development board. Subsequent posts can be found under the RISC-V Bytes category. I’ve been using the Pinecil as my primary soldering iron for a few months now. The neat thing about the Pinecil is that it is not only a highly portable USB-C powered iron,...
I spent the final week of 2022 feeling extremely sick, mostly confined to a bed. I was particularly disappointed in getting sick at that point in the year given that I was wrapping up the best running year of my life. I was very consistent with training, ran a few races, and was closing in on 1,400 miles. I am a big proponent of setting ambitious...
In my last post, we explored how to build WASM modules, both with and without WASI support, using Clang. In a comment on Reddit, it was mentioned that much of the setup I walked through in that post could be avoided by just leveraging Zig’s WASI supprt. This is a great point, and I would recommend doing the same. The following command is...
I am currently working on a few projects that involve leveraging WebAssembly (WASM) modules, particularly with WebAssembly System Interface (WASI) support. While WASI is still in its early stages, support has already been added to the Rust compiler and Clang, as well as runtimes such as wasmtime and WAMR. However, getting an environment setup to...
Screenshot of Badgecase gallery page. The final day of Supercon 2023 had more great talks, including an incredible recollection of Restoring the Apollo Guidance Computer. However, the real highlight was seeing all of the various badge hacks starting to take their final form, ultimately culminating with the Badge Hacking Ceremony at the end of the...
The energy from Friday at Supercon 2023 carried over into Saturday, and adding a stream of ongoing talks to the badge hacking and hallway track made it feel like even more was going on. The setup today was the traditional Supercon “hacker alley”, with the two talk venues connected by a long, narrow corridor packed with people, parts, and...
Just a few minutes after arriving at Hackaday Supercon 2023, I decided that I needed to document my experience. Working with two longtime Supercon veterans (they literally started the thing!), I had been adequately prepared for experiencing the event for the first time, but there is nothing quite like actually being there in-person. Even at 9 AM...
I have been using Vivado for moss RTL development, which, despite its notoriously large install size, offers a fairly decent developer experience. Or maybe I have just been using it for too long. I’m not sure I would have said this a few months ago. However, I still prefer to write Verilog in Neovim, as it allows me to use vim motions, as well as...
Most seasoned Go programmers are familiar with the memory representation of an interface. In fact, A Tour of Go, the canonical starting point for new Go programmers, makes sure to describe how interface values contain a value and a type (for a more specific description, see Russ Cox’s blog post on how interfaces are implemented), and even goes so...
If you are interested in what went into writing this blog post, you can view a replay of the livestream here. In a recent post we explored when Vivado inferred Block RAM (BRAM) for memories in FPGA designs, and when it used distributed RAM instead. While it is somewhat obvious why BRAM can be used for memory in an FPGA (i.e. it is literally a...
This is less of a blog post, and more of a collection of Friday thoughts that occurred to me on my morning run. Last night I was livestreaming some work on a new moss blog post in which I describe the use of Look-Up Tables (LUTs) as storage elements on an FPGA (this will be published in a few days). However, I ended up spending the majority of...
If you are interested in what went into writing this blog post, you can view a replay of the livestream here. As I’ve been working on the logic design for moss, I have been regularly investigating how Vivado translates the Verilog RTL (Register Transfer Level) source into Basic Elements of Logic (BELs), a process known as synthesis. BELs...
I have not been able to make as much progress on moss over the last 14 days or so as I would like, in large part because of limited time due to getting some exciting work across the finish line at $dayjob. However, whenever I find myself limited in the amount of “hands on keyboard” time I have to spend on a project, I try to invest more of my...
As I work on moss and research modern processor design patterns and techniques, I am also looking for patterns and techniques from the past that, for one reason or another, have not persisted into our modern machines. While on a run this week, I was listening to an old Oxide and Friends episode where Bryan, Adam, and crew were reminiscing on the...
Note: while I was writing this post, Julia Evans published a wonderful entry on her blog entitled Some tactics for writing in public. I highly recommend reading as it includes some wonderful guidance about how to preempt some of the discussion I reference in this post, as well as a short but highly relevant section on analyzing negative comments....
It’s a simple question really: how can you read and write to the same register in a single-cycle processor? If you have spent most of your life working with software, it is tempting to think of all events as happening sequentially. However, that sequential model that we have become so familiar with as software engineers is really an abstraction...
If you read most literature about processor design, you’ll inevitably be presented with three broad categories of CPU architectures: Single-Cycle Multicycle Pipelined We’ll just be focusing on the first two for today. In fact, my favorite introductory book on computer architecture, Computer Organization and Design (Patterson & Hennessy)...
TL;DR: even if you’re not being pragmatic, you probably don’t need to. One of the things I have been thinking about while starting to work on moss again is whether I should implement one of the many RISC-V flavors, or whether I should design an entirely new instruction set architecture (ISA). Designing a new one might seem like the ultimate...
I turn 27 years old today, which feels both very old and very young. 30 is often seen as a milestone, perhaps because you have spent nearly a decade operating as an “adult”, but likely are still considered in the earlier part of your career. I am a firm believer that doing most things of significance takes at least 3 years, which makes 27 a good...
Note: all analysis and code samples used in this post correspond to the v3.3.0 release of Zephyr. Having a good debugging workflow is critical to developing software quickly with high confidence. Fortunately, writing software for computers is often done, well, on a computer, meaning that while writing programs we can run other programs that help...
In the last two posts in the RISC-V Bytes series we have looked at a bootloader for the ESP32-C3, then built a Zephyr application that was loaded by it. In this post we’ll take a closer look at that “Hello, World” application, diving into what happens prior to printing our message to the UART console. Note: all analysis and code samples used in...
In the most recent post in the RISC-V Bytes series, we had our first experience with real hardware, exploring the bootloader on an ESP32-C3-DevKitC-02 module. We were using esp-idf, which, behind the scenes uses an implementation of FreeRTOS. In this post, we’ll swap out the Espressif FreeRTOS implementation for Zephyr, exploring some...
I recently acquired an ESP32-C3-DevKitC-02 module, and, as I tend to do, jumped right into reading about how the system boots and how the (pretty good!) tooling Espressif offers works. We have typically used QEMU in the RISC-V Bytes series, but getting our hands on physical hardware starts to make things feel a bit more real. In this first post...
Upbound reached General Availability on Tuesday and today is my last day at the company. It feels surreal to write that, despite knowing this day was coming for quite some time. With my time coming to a close, I wanted to take a moment to reflect on one of the most wonderful and impactful experiences of my life.1 Joining Upbound Link to heading...
Don’t have time to read this post? I get it. The answer to your question is /var/lib/kubelet//volumes/. Every so often I will be pairing with someone or showing off a demo and realize that some common operation I perform is not well-documented. We all have examples of domain knowledge we learned somewhere along the way and stashed in our toolbox....
In our most recent post in the Kubernetes API Server Adventures series we took a look at the storage interface and explored the only in-tree implementation: etcd3. However, a careful read of the footnotes in that post revealed I wasn’t being completely honest about etcd3 being the only implementation. This could be disputed as Cacher is...
Like most API servers, a, if not the, primary function of the Kubernetes API Server is to ingest data, store it, then return it when requested. Today we are going to be focusing on how the API Server stores data. Table of Contents: The apiserver Module (👈 “I want all the details.”) The storage Package Our Good Friend etcd The API Server and etcd...
Kubernetes is comprised of a variety of components, yet most end-user interaction with the system flows through the API Server. It is the entrypoint to many of the features that the project has built up over its lifetime, and can be extended to support arbitrary additional functionality. Because of this, the API Server has proved to be a...
Operating systems do great work, but sometimes they need a little bit of help to know when to switch from one task to another. Thankfully, hardware is there to help! Today we are going to take a look at how operating systems schedule reminders for themselves using timer interrupts. Sections Link to heading Don’t care about the why and just want...
Twitter has been a huge part of my online community, but it has become untenable as a platform. I have found a nice community of folks over on the types.pl server. I would love to reconnect with all of the wonderful people I have interacted with on Twitter and elsewhere. You can find me at @hasheddan@types.pl!
In our last post in the RISC-V Bytes series, I briefly alluded to the proposal to switch the Go Application Binary Interface (ABI) from a stack-based calling convention to a register-based calling convention. I also mentioned that it appeared at that time that the RISC-V port would support the new calling convention as early as Go 1.19. Last...
If you write any code that deals with manual memory management, you are likely familiar with the concept of a “use after free” bug. These bugs can be the source of, at best, program crashes, and at worst serious vulnerabilities. A lesser discussed counterpart to use after free, is “use after return”. In some cases, the latter can be even more...
Today’s @risc_v Tip: If cross-compiling a dynamically linked program, then executing using binfmt_misc, you’ll need to both: Inform the OS where the dynamic linker resides (or invoke directly) Inform dynamic linker where other shared libraries reside (LD_LIBRARY_PATH) Original Tweet
As a relatively young person in the technology industry who is interested in low-level software and designing hardware, but spends most of my day job working on backend and distributed systems, I frequently find myself lamenting the fact that many folks in my generation mostly grew up in a world where compute is thought of more in terms of an...
The following is an aggregation of a Twitter thread I posted on April 14th, 2022. Ever wondered how to open a UDP socket in @risc_v assembly? Wonder no more! li a0, 2 li a1, 2 li a2, 0 li a7, 198 ecall Let’s walk through it! 👇🏼🧵 The first thing to understand is that we are just a “normal” program running in user space. We don’t have special...
I usually write about deep technical topics, frequently going into extreme detail about how systems work. I love a good technical challenge, but recently the most challenging thing I have been working on at my day job has not been technical. Achieving Outsized Impact Link to heading I joined Upbound essentially straight out of college after...
Sometimes I hear folks in the Crossplane community ask if they can just use Helm instead of opting into our package manager. The technical answer to this question is “yes”, but it typically represents a misinterpretation of what Crossplane is providing in a Kubernetes cluster. That being said, I completely understand why someone would ask this...
This is part of a series on the blog where we explore RISC-V by breaking down real programs and explaining how they work. You can view all posts in this series on the RISC-V Bytes page. Today we are going to take a brief detour from our previous posts in this series and look at Rust Cross-Compilation for RISC-V. This will be a shorter post...
Tonight’s @risc_v Tip: The A extension defines 2 types of instructions for atomic operations: load-reserved/store-conditional (LR/SC) and atomic fetch-and-op (AMO). Both support acquire and release bits to impose additional ordering semantics. LR/SC uses them as follows: Note that LR.rl should not be set unless http://LR.aq is also, and...
Today’s @risc_v Tip: The second PPO rule defines “Same-Address Load-Load” ordering. This rule serves to preserve “Coherence for Read-Read pairs” (CoRR), specifying that instructions in same hart reading same byte preserve order if return values were written by different mem ops. Original Tweet
Tonight’s @risc_v Tip: The first rule in RVWMO Preserved Program Order falls under the Overlapping-Address Orderings category and ensures that any loads or stores to a memory address are ordered before a subsequent store to an overlapping memory address. Original Tweet
Today’s @risc_v Tip: RISC-V defines its memory model (RVWMO) in the context of 3 orderings: Program Order: order of ops performed by a single hart Global Memory Order: order of ops performed by all harts Preserved Program Order: subset of program order respected globally This diagram is an abstract example, but the key points are illustrated:...
Tonight’s @risc_v Tip: The Zmmul extension species only the multiplication instructions from the M extension, allowing constrained RISC-V implementations to opt not to support division. The spec calls out FPGAs as an example, as many have built-in multiplier hardware. You’ll notice that MULW is only supported on RV64 implementations. This...
Today’s @risc_v Tip: Instruction-Address-Misaligned exceptions can occur when a control transfer instruction (e.g. branch / jump) provides a misaligned target. The base ISA specifies 4 byte alignment (IALIGN=32), but extensions (such as C) may relax to 2 bytes (IALIGN=16). Original Tweet
First @risc_v Tip of 2022! The final new extension added in the v1.12 Privileged Spec is “Fine-Grained Address-Translation Cache Invalidation” (Svinval). It breaks SFENCE.VMA into three distinct instructions, allowing for its operations to be more efficiently pipelined. Original Tweet
Today’s @risc_v Tip: Another new extension in the v1.12 Privileged Spec is “NAPOT Translation Continuity” (Svnapot), which allows a PTE to indicate a 64 KiB range with consistent “flags” (bits [5:0]). The lower bits of the VPN are used to replace indicator bits in PPN on read. Original Tweet
Today’s @risc_v Tip: A new version of the RISC-V Privileged Architecture (v1.12) was released on Dec 3rd. One of the larger changes is the addition of the “Page-Based Memory Types” extension (Svpbmt). It is configured in leaf PTE bits [62:61] in Sv39, Sv48, and the new Sv57. Original Tweet
Today’s @risc_v Tip: The Zifencei extension defines one instruction, FENCE.I, which orders memory writes and instruction fetches. Unlike FENCE, it only synchronizes instructions visible to a single hart. The rd / rs1 / imm[11:0] fields are reserved for future use. Original Tweet
Today’s @risc_v Tip: The FENCE instruction is defined as part of the base ISA and allows for explicit ordering of instructions prior to (“predecessor set”) and following (“successor set”). Types of instructions to be ordered are specified in each set using the P and S bits. Note that it is common to just see a plain fence in RISC-V assembly,...
This is part of a series on the blog where we explore RISC-V by breaking down real programs and explaining how they work. You can view all posts in this series on the RISC-V Bytes page. It has been a bit since our last post, but today we are going to begin our journey into some of the more interesting areas of RISC-V systems. In the first post in...
Tonight’s @risc_v Tip: Implementations may define an arbitrary number of Non-Maskable Interrupts (NMIs). NMIs cannot be disabled and must only be used to represent hardware errors. The mcause CSR may be updated to specify a dedicated interrupt code, or otherwise must be 0. Original Tweet
Christmas @risc_v Tip: The Zicsr extension defines instructions for clearing and setting CSR bits, which are abstracted by the pseudoinstructions csrc and csrs. Example tandem usage below with bit masks (t0 / t1) to set “Machine Previous Privilege” (mstatus[12:11]): Original Tweet
Today’s @risc_v Tip: The trap vector BASE address CSRs (mtvec / stvec) can use the lowest two bits for MODE because the BASE address must be 4-byte aligned (i.e. lowest two bits = 00). Note that a non-masked write of a valid address will overwrite MODE to Direct (00). Original Tweet
Today’s @risc_v Tip: If using ld as your linker, a global symbol defined as start will take precedence over earlier symbols in your .text section for program entry point when explicit ENTRY is not defined in your script or via -e flag on the command line. Original Tweet
Today’s @risc_v Tip: Traps become more complicated in a pipelined implementation if exceptions occur after subsequent instructions have been issued. The sepc CSR holds the address of the offending instruction, but an implementation may choose whether it is precise or not. Original Tweet
Tonight’s @risc_vTip: Understanding marketing material for processors can be confusing. @SiFive recently released its highest performance RISC-V processor: P650. Let’s break down what it broadly means to be a “thirteen-stage, four-issue, out-of-order processor”. Original Tweet
Today’s @risc_v Tip: Regularity is a key design principle of RISC-V and has a large impact on implementation complexity. Fields always reside in the same location when present in an instruction, meaning that generic decode can be performed regardless of the eventual operation. Original Tweet
Tonight’s @risc_v Tip: Atomicity Physical Memory Attributes (PMAs) specify support for atomic instructions described in the A extension in the Unprivileged Spec for a given range. There are two types: Atomic Memory Operations (AMO) Load Reserved / Store Conditional (LR/SC) Original Tweet
Tonight’s @risc_v Tip: Physical Memory Attributes (PMAs) define the capabilities of a given address range. A range may be mapped to main memory, I/O devices, or may be empty. PMAs include: Access Type Atomicity Memory-Ordering Coherence / Cacheability Idempotency Original Tweet
Today’s @risc_v Tip: The address of a Control and Status Register (CSR) encodes access and privilege level in the top 4 bits. CSRs are accessible at their privilege level + all higher privilege levels. The Use bits further segment address space into Standard and Custom CSRs. Original Tweet
Today’s @risc_v Tip: Today’s tip comes courtesy of the OpenTitan (a @lowRISC project) RISC-V assembly style guide. Using n(reg) offset syntax (even if n=0) when interacting with registers that are storing pointers makes it visually clear that the contents are a memory address. Original Tweet
Tonight’s @risc_v Tip: MIT’s xv6 teaching OS is a great introduction to RISC-V. For example, start() contains most of the logic required to jump from Machine (M) mode to Supervisor (S) mode. Original Tweet
Tonight’s @risc_v Tip: RISC-V contains a few interrupt controller specs, each providing additional functionality over basic privilege-based preemption: Core-Local Interrupt Controller (CLIC) Platform-Level Interrupt Controller (PLIC) Advanced Interrupt Architecture (AIA) The Advanced Interrupt Architecture (AIA) spec encompasses two different...
Today’s @risc_v Tip: The RISC-V Hypervisor extension recently reached v1.0 and was ratified. Hypervisor (HS) mode extends Supervisor (S) mode with additional CSRs and instructions, allowing for two additional privilege levels: Virtual Supervisor (VS) and Virtual User (VU). Original Tweet
Tonight’s @risc_v Tip: Come join me (virtually or in person) on Monday to kick off #RISCVSummit! We’ll be talking about @crossplane_io and how open hardware fits into the open cloud 🏗 Schedule Original Tweet
Tonight’s @risc_v Tip: The Supervisor Trap Base Address CSR (stvec) indicates the location of the Supervisor (S) trap handler(s). The BASE address may be virtual or physical, and two modes are supported, with “Vectored” allowing for different handlers for each interrupt type. Original Tweet
Tonight’s @risc_v Tip: Supervisor (S) mode has a dedicated memory-management (mm) fence instruction (SFENCE.VMA) that ensures visible stores are ordered before subsequent implicit references to mm data structures. The values of registers in rs1 and rs2 dictate behavior. Original Tweet
Tonight’s @risc_v Tip: Sv32 supports a 2-level page table, but any Page Table Entry (PTE) may be a leaf. Page tables are the size of a page, so a leaf level 1 PTE corresponds to a “megapage” (4 MiB). 1 Page = 4 KiB 1 PTE -> 1 Page 1 Page Table -> 1024 PTE 4 KiB * 1024 = 4 MiB Errata: Small correction to diagram: VPN[0] is used to populate PPN[0],...
Tonight’s @risc_v Tip: Sv32 uses a two-level page table to enable virtual memory. A virtual address contains two Virtual Page Numbers (VPN) and an offset. The Physical Page Number (PPN) of the leaf Page Table Entry (PTE) is combined with the offset to form the physical address. Original Tweet
Bonus Holiday @risc_v Tip: If the SUM bit in the sstatus CSR is 0, a PTE with U=1 means the page is not accessible from Supervisor (S) mode. If SUM=1, supervisor access is permitted. A supervisor may never execute code from a page accessible from User (U) mode. Original Tweet
Tonight’s @risc_v Tip: A 32-bit Page Table Entry (PTE) in Sv32 virtual memory mode contains four bits that indicate access permissions. The R, W, X bits correspond to Read, Write, and Execute access respectively. The U bit indicates whether the page is accessible in User (U) mode. Original Tweet
Tonight’s @risc_v Tip: The satp CSR configures Supervisor (S) mode address translation and protection. RV32 and RV64 support different sets of virtual addressing schemes, which can be configured by writing MODE bits. Writing an unsupported scheme is ignored (WARL). Original Tweet
Today’s @risc_v Tip: Our last PMP addressing mode is Top of Range (TOR). A TOR entry forms an address range from the preceding entry’s pmpaddr (inclusive) to its pmpaddr. If a TOR entry is in the first pmpconfig CSR, the bottom bound of its address range is 0. Original Tweet
Tonight’s @risc_v Tip: Physical Memory Protection (PMP) and page-based virtual memory are designed to work together. Accessing virtual memory sometimes results in physical memory accesses. In those situations, the physical memory accesses are checked against PMP entries. Original Tweet
Tonight’s @risc_v Tip: Looking again at Physical Memory Protection (PMP) address matching modes, Naturally Aligned Powers of Two (NAPOT) addressing allows you to specify ranges with four-byte granularity by encoding the size in the low-order bits of the pmpaddr CSRs. Original Tweet
Tonight’s @risc_v Tip: Yesterday we talked about the Physical Memory Protection (PMP) unit. PMP entries are defined with separate config and address CSRs. The 8-bit config CSR for an entry dedicates 2 bits (A) to defining the matching mode of its address CSR. Original Tweet
Tonight’s @risc_v Tip: An optional Physical Memory Protection (PMP) unit is defined that enables memory access control for software on a given hart. This is accomplished through a set of configuration and address CSRs, and applies to all accesses with effective mode of S or U. Original Tweet
Tonight’s @risc_v Tip: You might assume some exceptions, such as an ecall from User mode (U), are handled in Supervisor mode (S), but all traps are handled in Machine mode (M) by default. However, the medeleg CSR can be used to delegate some traps to a lower privilege level.. Original Tweet
Tonight’s @risc_v Tip: Continuing with the Trigger Module (TM), the RISC-V debug spec provides access to triggers via the tselect and tdata1 / tdata2 / tdata3 CSRs. A list of supported triggers for a hart can be obtained by a sequence of write / read back operations. Original Tweet
Today’s @risc_v Tip: RISC-V has a separate debug spec that defines a Debug Module (DM), Debug Module Interface (DMI), Debug Transport Module (DTM), and Trigger Module (TM). The TM can be implemented independently of a DM, and adds support for setting native hardware breakpoints. Original Tweet
Tonight’s @risc_v Tip: If you have ever worked with low-level programming, you may be familiar with the ambiguity of the terms exception / interrupt / trap. RISC-V clearly defines each in the unprivileged spec (S 1.6), with the definitions adhering to the IEEE-754 standard. Original Tweet
Tonight’s @risc_v Tip: The GNU assembler (gas) supports a few specific RISC-V directives, including .option, which allows you to modify assembler options inline. A common use case: temporarily disabling relaxation to perform initial global pointer load into gp register. Original Tweet
Tonight’s @risc_v Tip (feat. @golang): Go uses a compare and swap (CAS) implementation similar to the example provided in the RISC-V unprivileged spec. The Go assembler always uses acquire access (aq=1) to align with the language’s memory requirements. Original Tweet
This post references the Kubernetes codebase at commit d92a443ca7 and kube-openapi at commit ee342a809c, but should remain mostly applicable for an extended period of time barring any massive refactor to Kubernetes internals. This is also intended to be a very active read and a reference to come back to over time. There are a lot of links to...
Tonight’s @risc_v Tip: You can use two convenient pseudo-instructions to load the address of a symbol into a CSR. la t1, main => auipc t1, main[31:12]; addi t1, t1, main[11:0] csrw mepc, t1 => csrrw x0, mepc, t1 Original Tweet
Tonight’s @risc_v Tip: You can list all the harts on the platform you are debugging with gdb using info threads. Switching to another hart can be done with thread . A quick way to check the current hart is to display the contents of the mhartid CSR. Original Tweet
Today’s @risc_v Tip: The mcause (M) / scause (S) CSRs indicate what type of exception caused a trap to the respective privilege level. A single instruction could cause multiple synchronous exceptions, in which case the register indicates event with the following priority: Original Tweet
This post explores what a future of shipping infrastructure alongside software may look like by detailing where we are today, and evaluating how the delivery of software has evolved over time. If you just want the big ideas, skip to the final section: A New Kind of Software Marketplace. Almost all software depends on infrastructure. Installation...
Today’s @risc_v Tip: The 8th bit in the Supervisor (S) Status (sstatus) CSR is called the SPP bit and indicates the hart’s privilege level before entering S mode. 0 indicates User (U) mode, and 1 indicates other. An sret instruction changes mode to U if SPP is 0 and S if 1. Original Tweet
Today’s @risc_v Tip: Machine (M) mode supports hardware performance monitoring (HPM) with the following CSRs: mcycle: number of clock cycles executed minstret: number of instructions retired mhpmcounter[3-31]: event counters mhpmevent[3-31]: event selectors Original Tweet
Today’s @risc_v Tip: The satp (Supervisor Address Translation and Protection) CSR contains virtual memory translation information, including MODE. Valid modes for RV32 & RV64 include: RV32: Bare / Sv32 RV64: Bare / Sv39 / Sv48 Bare indicates no translation or protection. Original Tweet
Today’s @risc_v Tip: RISC-V systems may support 3 main privilege levels: Machine (M) (Req.) Supervisor (S) (Opt.) User (U) (Opt.) Execution context changes via traps. A trap that moves to a higher privilege level is a vertical trap, one that does not is a horizontal trap. Original Tweet
Today’s @risc_v Tip: Fields of CSRs adhere to one of the following behaviors: WIRI: Reserved Writes Ignored, Reads Ignore Values WPRI: Reserved Writes Preserve Values, Reads Ignore Values WLRL: Write/Read Only Legal Values WARL: Write Any Values, Reads Legal Values Original Tweet
Today’s @risc_v Tip: You likely think “Hardware Security Module” when you see “HSM”. When working with RISC-V systems you’ll frequently see the term “Hart”, which is a “Hardware Thread”, and in related contexts “HSM” will typically refer to “Hart State Management”. Original Tweet
QEMU @risc_v Tip of the Night: Running without -bios specified or with -bios default will automatically load the OpenSBI binary. Original Tweet
GDB tip of the day: info registers will show you the contents of general purpose registers, but info all-registers will expand the output to floating point registers and CSRs. Original Tweet
This is part of a series on the blog where we explore RISC-V by breaking down real programs and explaining how they work. You can view all posts in this series on the RISC-V Bytes page. So far in this series, we have been looking at the assembly generated when compiling relatively simple programs. At this point, we have seen instructions that...
I am excited to announce the launch of the Research Triangle RISC-V Community Group! As evidenced by my recent posts and conference talks, I have been spending more and more time learning and working in and around the RISC-V community. While there are numerous commercial benefits of an open source instruction set architecture (ISA), I am...
This is part of a series on the blog where we explore RISC-V by breaking down real programs and explaining how they work. You can view all posts in this series on the RISC-V Bytes page. I once took a class on compilers where my professor told us that a CPU is like a human brain: it can store important data and access it quickly, but there is a...
This post is adapted from my message sent to the Kubernetes SIG Release mailing list. I got involved in the Kubernetes community right after finishing school, primarily by working on the tooling used to test and release each of the components of the project. From the beginning, I was shown a tremendous amount of respect and care, and that has...
This is part of a new series I am starting on the blog where we’ll explore RISC-V by breaking down real programs and explaining how they work. You can view all posts in this series on the RISC-V Bytes page. When looking at the generated assembly for a function, you may have noticed that the first few instructions involve moving values from...
This is part of a new series I am starting on the blog where we’ll explore RISC-V by breaking down real programs and explaining how they work. You can view all posts in this series on the RISC-V Bytes page. To start of the series, we are just going to get setup to do some exploration. I am going to assume you will not primarily be using a RISC-V...
For folks familiar with Crossplane, you likely know that we adopt the design practice of using interfaces over implementations as frequently as possible. Even if we begin with an implementation, such as the current composition engine, we make sure to consider a future with potentially many implementations for the same functionality. One of the...
This post describes a breaking change in runc v1.0.0-rc93, that has subsequently had a workaround implemented that will presumably be included in v1.0.0-rc94. Thanks to @haircommander for talking through the issue with me and implementing the subsequent workaround, and to @mattomata for his consultation on the distroless/static:nonroot behavior....
If I was to explain LLVM in a painfully simple manner, I might say something like: “LLVM is a framework that allows you to define a syntax for interacting with computers, and instantly have it work for all computers”. This description does a colossal disservice to the scope of the project, but it serves to illustrate the basic idea: there are...
controller-runtime exposes a metrics server by default on port 8080 for any controller Manager. Metrics are registered for the client, workqueue, and on a per-controller basis. Controllers initialize metrics when started, and write to the registry at various points throughout operation, such as when processing items off the workqueue and after...
If you have written a Kubernetes controller, you are likely familiar with controller-runtime, or at least client-go. controller-runtime is a framework for building controllers that allows consumers to setup multiple controllers that are all handled under a controller manager. Behind the the scenes, controller-runtime is using client-go to...
I had the privilege of joining Steven Borrelli from Mastercard for a tutorial at Kubecon North America 2020 on building an enterprise infrastructure control plane on Kubernetes using Crossplane. Relevant links and the talk recording can be found below. Slide Deck Source Code Text Transcript Please feel free to send me a message @hasheddan on...
Vivado is Xilinx’s IDE for HDL synthesis and analysis. It is a powerful tool, but can be a bit of a pain to setup and use. I recently went through the installation process on my main development machine, where I cam currently running Ubuntu 20.04, after I purchased a Digilent Arty A7-35T development board, which is designed around the Xilinx...
The following is an unroll of a tweet thread about Crossplane packages that I posted after reading Dave Anderson’s post “A better Kubernetes, from the ground up”. I found many of the points in the post compelling, but feel that the existing extensibility model of Kubernetes allows for implementing at least some of the desired features without...
This post explores RISC-V assembly by examining the implementation of the setjmp and longjmp functions from the C standard library. I frequently find that I grasp concepts more quickly when I have actual code that I can disassemble because it allows me to connect information with intent. I believe RISC-V and similar efforts will fundamentally...
I joined Scott Lowe on the Full Stack Journey podcast for a chat about how Crossplane enables you to provision infrastructure from your Kubernetes cluster and allows you to compose abstractions that define your own PaaS. You can listen here.
If you have ever written assembly for the GNU Assembler (GAS), you may have noticed that files sometimes have an .S extension and sometimes .s. This is not a meaningless distinction, and you could have a frustrating time if you accidentally use the wrong one. The uppercase .S indicates that the file contents should be run through the...
I joined Rin Oliver on the esper.io DroidDevCast for a chat about rapid prototyping. You can listen here.
I joined Daniel Bryant on the Ambassador Livin’ on the Edge podcast for a chat about Crossplane, building your own PaaS, and the future of multi-cluster Kubernetes. You can listen here.
I had the opportunity to write up a recap and guide for the livestream I did with Alex Ellis on using Crossplane with OpenFaas. It is available here.
I had the privilege of writing a guest post on the AWS Open Source Blog entitled “Connecting AWS managed services to your Argo CD pipeline with open source Crossplane”. You can read it here.
Jared Watts, Marques Johansson, and I sat down for a chat about Crossplane and the cloud native community with Gerhard Lazu on the Changelog Podcast at Kubecon North America 2019. You can listen here.
Note: While writing this post, I looked back at a post I wrote entitled Understanding ETL to ELT by Going to Costco. That post does exactly what I say we should not do in this post. It takes a process and explains it using a metaphor that cannot hope to fully encompass what I try to say. I do think that metaphors can be somewhat useful when...
This is the first installment of HashiCode, a blog post series where I go through the source code of HashiCorp tools to learn more about what happens behind the scenes when you interact with tools as a user. Disclaimer: this episode is referencing code from the Terraform codebase as of commit 43a7548. Becuase Terraform is a constanly evolving...
Today I am excited to announce a new series of blog posts called HashiCode. I have been involved with the HashiCorp community for some time now, and I have loved the opportunity to contribute to some of my favorite tools because of the open source model of the company. Recently, I have been organizing the new HashiCorp User Group in St. Louis, a...
Sometimes I find it hard to focus on the work I am doing. It can be easy to constantly be evaluating how everything you are doing affects the present, affects your future, and affects those around you. These are good questions to be asking, but at the right time. If we are always planning, how are we ever going to get anything done? On the other...
If you have dealt with any data platform in the last few years, you have likely heard about the movement from traditional ETL (Extract Transform Load) to ELT (Extract Load Transform). The name ELT is self-explanatory as the sequential order of tasks is switched such that loading comes before the transformation, but it takes a little more...
I passed the AWS Solutions Architect Associate Certification Exam today and I wanted to write up a few immediate thoughts because I still feel as though the process is somewhat opaque for most people. Part of this may be because of the NDA that you are required to agree to prior to taking the exam. To be clear, everything mentioned in this post...
^Run-Time (I admit that the title is intended to be clickbait) CloudFormation has become a popular Infrastructure as Code (IaC) tool for organizations that use AWS exclusively as their cloud provider (whether it should be or not is another whole discussion). The tool features the ability to add parameters to your configuration scripts (written in...
Building apps using Ionic is useful for the ability to build for both IOS and Android from the same codebase. However, mostly because Ionic is build on top of the Apache Cordova framework, it can be difficult to make sure your environment is configured with the required version of each build component. This is where Docker can be helpful. You can...
Docker containers are widely used for developing and running anything from web applications to redis caches. However, they can also be useful for running what can effectively be a light VM (a container operates very differently from a VM, but we are just talking about the use case). I like to use a container for accessing the the Linux command...
This guide will teach you how to run the Kong API gateway locally as a proxy server for a Golang API using Docker. The Go API Link to heading The Golang standard library has a very simple http library that makes it very easy to spin up a web server. For now, we will build the simplest implementation of a web server. Start by creating a new...
I have always been envious of developers who share valuable information on their blog. I have thought for a long time that I wanted to be one of those developers that became famous in programming circles for the insight they shared. However, this also led me to be intimidated by the idea of writing my own posts. How could I ever measure up to...
My name is Daniel Mangum and I am a principal software engineer at Upbound where I have helped build Upbound Cloud, Upbound Marketplace, and the open source Crossplane project. I have worked in multiple other open source communities, including holding leadership positions in the Kubernetes project. I am primarily interested in distributed...