4-Byte Aligned Trap Vectors

from blog Daniel Mangum, | ↗ original
Today’s @risc_v Tip: The trap vector BASE address CSRs (mtvec / stvec) can use the lowest two bits for MODE because the BASE address must be 4-byte aligned (i.e. lowest two bits = 00). Note that a non-masked write of a valid address will overwrite MODE to Direct (00). Original Tweet