Identifying Debug Triggers

from blog Daniel Mangum, | ↗ original
Tonight’s @risc_v Tip: Continuing with the Trigger Module (TM), the RISC-V debug spec provides access to triggers via the tselect and tdata1 / tdata2 / tdata3 CSRs. A list of supported triggers for a hart can be obtained by a sequence of write / read back operations. Original Tweet