When Does Vivado Infer BRAM?

from blog Daniel Mangum, | ↗ original
If you are interested in what went into writing this blog post, you can view a replay of the livestream here. As I’ve been working on the logic design for moss, I have been regularly investigating how Vivado translates the Verilog RTL (Register Transfer Level) source into Basic Elements of Logic (BELs), a process known as synthesis. BELs...