SuperComputing 19: HPC Meets Machine Learning

The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs through extensive design co-optimization, adoption of new materials, and judicious use of EUV lithography. The first product, the Meteor Lake compute tile, will ramp to high volume manufacturing in 2023. The post Intel 4 Process Scales Logic...

Transistor count and transistor density are often portrayed as technical achievements and milestones. Many vendors brag about the complexity of their design, as measured by transistor count. In reality, transistor count and density varies considerably based on the type of chip and especially the type of circuitry within the chip, and there is no...

Power delivery is one of the most significant challenges in modern processors. The power delivery network (PDN) must meet the demanding requirements of modern CMOS technology, supply power with excellent efficiency, and swiftly respond to changes in power draw. The post Power Delivery in a Modern Processor appeared first on Real World Tech.

At VLSI 2018, researchers from TDK and TSMC described advances in Magneto-resistive memory (MRAM). TDK focused on new materials to improve writing for low-voltage MRAM cells at small geometries. A team from TSMC showcased circuit techniques to improve read performance of MRAM arrays despite process variability and a small read window. The post...

IBM presented a neural network accelerator at VLSI 2018 showcasing a variety of architectural techniques for machine learning, including a regular 2D array of small processing elements optimized for dataflow computation, reduced precision arithmetic, and explicitly addressed memories. The post IBM’s Machine Learning Accelerator at VLSI 2018...